FIG. 1 depicts a block diagram of a typical buck converter with N phases and FIG. 2 illustrates the yield of a four-phase buck converter, i.e. of the output current and of the number of active phases (PH). For this reason, multi-phase voltage converters are controlled to adapt the number of active phases to the external load conditions, by reducing or increasing the number of phases depending on the current being delivered by the converter.
A problem tied to the reduction of the number of functioning phase circuits is to reduce as much as possible the undershoot of the output voltage during these transitions. In order to understand what causes the undershoot of the output voltage, reference is made to FIG. 3 that illustrates an exemplary transition from three active phases to one active phase circuit. IL1, IL2 and IL3 represent the currents through the inductors, IOUT represents the sum of the currents through the inductors (the dashed part indicates the ideal IOUT during the transition), and ILOAD represents the current used by the load and PS (Power Saving) a signal that enables the reduction of the number of active phase circuits.
As far as PS=0, the output sum current IOUT has an “updating” frequency equal to N*FSW, wherein FSW represents the switching frequency of the single stage and N represents the number of phases of the system. In particular, during each IOUT cycle, equal to TSW/N, wherein TSW is the switching period of a single phase circuit, it is possible to identify a charge time during which there is always at least a phase circuit that is on and the other phase circuits are off, and a discharge time during which the other two phase circuits are off. When PS=1 (instant t0), the phase circuits that may be turned off could be driven with a null duty-cycle (the low side MOS is on), as far as the respective phase currents cancel out (instants t2 and t3, respectively).
During the interval t0-t2, when the phase current LL3 is canceled and the phase current IL1 is not yet in a steady-state condition, the equivalent switching frequency FEQ on the output current IOUT reduces (in this case FEQ=3*FSW) compared to the frequency that was present when the signal PS was logically low. This results in a drop of the equivalent output current IOUT compared to that requested by the load ILOAD. The area QT represents the charge lost by the output filter COUT during the transition that causes the voltage drop, which may depend on the output capacitance being used.
During the interval t2-t3, when the phase current IL2 is canceled out, the nominal equivalent switching frequency of a converter with two active phases and one phase off, i.e. FEQ=2*FSW, is not attained, thus causing a further charge loss on the output filter. When the phase current IL2 becomes null (instant t3), the equivalent frequency is FSW, i.e. the frequency of a converter with a single active phase circuit (mono-phase). The consequent drop of the output voltage becomes more relevant and the converter may compensate it in a slower or faster way depending on the bandwidth of the single phase circuit.
It may be important to eliminate, or at least limit, the output voltage undershoot during those transitions for not disturbing the functioning of the voltage control loop of the converter that intervenes for compensating the disruption. The greater the load current during the transition, the larger the current drop IOUT. FIG. 4 illustrates a transition from three phases to one phase in low load conditions. Differently from the example of FIG. 3, the lost charge QT during the transition is smaller than in the previous case because the currents through the phase circuits to be turned off are almost null.
Sometimes, for simplifying the design, the phases to be turned off are set to a high impedance state as soon as PS=1. In this case, the currents are discharged with a larger slew rate because the free-wheeling diode of the low side MOS of the phase is turned on. As a result, additional charge is lost from the output filter capacitance, as shown in FIG. 5, wherein the dashed parts indicate the transition shown in FIG. 3, with the low side MOS turned on. This approach, besides generating a large undershoot of the output voltage, causes a loss of efficiency of the converter under medium load conditions and in case of switching to and resuming from a power saving mode because, while turning off the phases, the free-wheeling diodes of low side MOS switch on, thus dissipating power.
According to another typical technique, illustrated in FIG. 3, the low side MOS of the phases to be turned off is kept on until the current nullifies or reaches a pre-established threshold. This approach may be better than the previous one from the point of view of power dissipation, but implies a significant drop of the output voltage. A feedback voltage converter, a block diagram of which is depicted in FIG. 6, is illustrated in the published U.S. Patent Application Publication No. 2008/0272752 to Qiu et al. FIG. 7 illustrates an exemplary time diagram of the converter of FIG. 6 in the case in which six phase circuits are present. The signal PSI# is the logic switching signal, P1, P2, . . . , P6 are the enabling signals of the respective phase circuits. In the last figure, there are two extra pulses that are added in correspondence of the enable pulse of the phase circuit 4 to sustain the output and to speed up the phase dropping transient. The equivalent frequency of the converter during the transition is twice the nominal frequency of the phase current IL1 when the phase current IL2 is not null as well as when the phase circuit is in a high impedance state with a null current (the phase circuit IL2 is off).
FIG. 8 illustrates a transition from six active phase circuits to two active phase circuits with a single pulse addition for each phase circuit. As shown, the two active phase circuits are not outphased by 180 degrees as it would be desirable in a two-phase converter. In the simulation illustrated in FIG. 9 of a three phase system, only a pulse is added because the output current is already low. The above-discussed prior patent publication is silent about the criterion used for determining the number of pulses to be added.